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Precharge command
Pre-charge command is used to pre-charge both the bit lines to VDD/2.

Row Activation
Row activation is performed by asserting the ~RAS and providing the row address of desired row. Asserting the ~RAS pre-charges both the bit lines to VDD/2 (with help of pre-charge circuit). In the mean time, the switch transistors for particular row start to conduct (switch turns on). This connects the capacitor cells to the positive bit lines. The potential on positive bit line changes (increases to VDD/2 + delta or decreases to VDD/2 - delta) based on the cell charge on capacitor. The voltage change on bit line is small because the cell capacitance is generally much smaller (generally fractions of pF) as compared to the capacitance of transistor and the bit line. Sense amplifier amplifies this small voltage difference to either VDD or Zero. The sense amplifier output gets latched (this latch has not been shown in the figure but it exists) and row activation is complete.

Column Read
Once the output from a given row is available at sense amplifiers, any of the columns can be read by enabling the Column Access (using ~CAS and column address) and ~OE. Reading multiple columns from same row is very easy. For accessing a cell from a different row, new row needs to be activated. Closing a row requires the cells of current row to be restored as we will discuss later.

Column Write
Column write involves forcing the bit lines to a desired voltage after row activation.

Row pre-charge
The reading operation discharges the capacitors cell of particular row. These capacitors need to be recharged after the read operation is over. This operation is called row pre-charge (do not confuse it with pre-charge command). The row pre-charge is not needed while performing successive read operations from the same row. When a read/write operation has to be performed from another row, the current row pre-charged.

Reading
* Row Activation
* Column Read
* Row pre-charge
Writing
* Row Activation
* Column Write

Row refresh
As we discussed before the capacitive storage cells leak charge. There is a need of periodically refreshing the rows. Row refresh involves row activation followed by row pre-charge (without enabling the ~OE or ~WE buffers). Generally the refresh period is of the order of few ms (64 ms being most common). There are two ways to implement auto-refresh. Either all the rows can be refreshed every 64ms. Or different rows can be periodically refreshed (one at a time) such that each row is refreshed every 64 ms. For example if there are 1024 rows, a row refresh can be performed every 62.5 us.

DRAM Variations

Asynchronous DRAM
This is the basic form, from which all others are derived.

Synchronous DRAM
SDRAM has a synchronous interface, meaning that it waits for a clock signal before responding to its control inputs. It is synchronized with the processor’s system bus. The clock is used to drive an internal state machine that pipelines incoming instructions. This allows the chip to have a more complex pattern of operation than asynchronous DRAM which does not have synchronizing control circuits. SDRAM can support burst mode accesses. SDRAM is also known as SDR SDRAM (single Data Rate SDRAM).

DDR SDRAM
DDR (Dual Data Rate) SDRAM achieves greater bandwidth than the preceding SDR SDRAM by transferring data on the rising and falling edges of the clock signal (double pumped). Effectively, it nearly doubles the transfer rate without increasing the frequency of the front side bus.

DRAM Interface
A SDRAM interface involves following common signals
~CAS
~RAS
~WE
~OE
Address Pins
Data Pins (bi-directional)
CLK and CLKEN (in case of SDRAM)
Power connections

DRAM Controller
Since the addressing scheme and read/write operations in an SDRAM are slightly different from that of an SRAM, these devices can not be directly interfaced to the processors which provide SRAM interface. A SDRAM controller needs to be used to control the operations of an SDRAM. Most modern processors have an in-built SDRAM controller. The SDRAM controller needs to be programmed with different parameters (like row size, column size, refresh period etc) before accesses to SDRAM can be made. The SDRAM parameters are dependent on SDRAM device being used.

Self refresh mode (for power down operations)
The Self-refresh mode can be used to retain data in the SDRAM, even if the rest of the system is powered down. An internal timer meets all the refresh requirements. This feature provides the capability to reduce power consumption during refresh operations. In self-refresh mode, the address buffer and command interface are disabled.

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